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Paper - II (viii) — Digital Logic Systems MCQ - Practice Questions with Answers

Solve 45 Paper - II (viii) — Digital Logic Systems questions for RAS/RPSC preparation.

Practice questions

Q1A full adder has inputs A, B and Cin. Which pair correctly gives its Sum and Carry output?

A Sum = A ⊕ B ⊕ Cin, Carry = AB + BCin + ACin

B Sum = AB + BCin + ACin, Carry = A ⊕ B ⊕ Cin

C Sum = A ⊕ B, Carry = Cin(A + B)

D Sum = A + B + Cin, Carry = ABCin

Explanation

A full adder adds three one-bit inputs. The Sum bit is 1 for an odd number of 1s, hence A ⊕ B ⊕ Cin. The Carry bit is 1 whenever at least two inputs are 1, represented by AB + ACin + BCin.

Q2Which step is essential when designing a synchronous sequential system from a state diagram?

A Assign binary codes to states, derive flip-flop excitation/next-state equations, and implement the resulting combinational logic.

B Minimize only the output equation and skip next-state equations.

C Ignore unused states because they can never affect hardware behavior.

D Connect all flip-flop clocks to different unrelated clock sources.

Explanation

A state diagram must be converted into hardware by encoding states, building the state table, selecting flip-flops, deriving excitation or next-state equations, and then realizing those equations with combinational logic feeding commonly clocked storage elements.

Q3For a half-subtractor with minuend A and subtrahend B, which pair gives Difference and Borrow respectively?

A AB, A ⊕ B

B A + B, AB

C A ⊕ B, A̅B

D A ⊕ B, AB

Explanation

A half-subtractor compares A - B. The difference bit is 1 when the inputs differ, giving A ⊕ B. Borrow is needed only for A = 0 and B = 1, which is represented by A̅B.

Q4In a full subtractor with inputs A, B and Bin, what is the correct expression for the Difference output?

A AB + Bin

B A + B + Bin

C A'B + AB'

D A ⊕ B ⊕ Bin

Explanation

A full subtractor computes A minus B minus Bin for one bit. The Difference output is the modulo-2 result, so it is 1 when an odd number of A, B and Bin inputs are 1. That is represented by A XOR B XOR Bin; borrow logic is handled by a separate output.

Q5In a full adder with inputs A, B, and Cin, which pair correctly represents Sum and Carry-out?

A Sum = A xor B; Carry = AB + Cin

B Sum = A + B + Cin; Carry = ABCin

C Sum = AB + BCin + ACin; Carry = A xor B xor Cin

D Sum = A xor B xor Cin; Carry = AB + BCin + ACin

Explanation

A full adder adds three one-bit inputs. The Sum bit is 1 for an odd number of 1s, giving A xor B xor Cin. The Carry-out is 1 when two or three inputs are 1, so it is the majority term AB + BCin + ACin.

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6For a three-variable function F(A,B,C) = Σm(1,3,5,7), what is the minimal SOP expression obtained from a K-map?

AA + C

CA̅C + AC

DB + C

7Why is a NAND gate called a universal gate in combinational logic design?

ABecause it has zero propagation delay in every logic family.

BBecause NOT, AND, and OR operations can all be constructed using only NAND gates.

CBecause it can store one bit of memory without feedback.

DBecause it requires no power supply in TTL and CMOS circuits.

8A JK flip-flop is used in a synchronous counter. Which input condition makes it toggle on the active clock edge?

AJ = 1, K = 1

BJ = 1, K = 0

CJ = 0, K = 0

DJ = 0, K = 1

9Which statement best compares standard CMOS and TTL logic families in normal digital IC usage?

ATTL and CMOS always use identical input threshold voltages for every supply voltage.

BTTL gates are MOSFET-based and normally draw almost no static input current.

CCMOS gates use complementary MOS transistors and typically have very high input impedance with low static power dissipation.

DCMOS logic is preferred only because it has no propagation delay.

10A synchronous sequential circuit is to be designed using D flip-flops. If the required next-state equation for one state bit is Q_next = XQ' + X'Q, what should be connected to the D input of that flip-flop?

AX + Q

BX ⊕ Q

CXQ

11Which statement best compares CMOS and TTL logic families in ordinary digital circuit design?

ACMOS generally has very high input impedance and low static power dissipation, while TTL uses bipolar transistor stages and draws more input/output current.

BCMOS and TTL always use identical input threshold voltages, so they can be mixed without checking logic levels.

CTTL gates have almost zero static power consumption because their inputs are insulated MOS gates.

DCMOS cannot implement NAND or NOR gates, so it is used only for memory cells.

12A 4:1 multiplexer has select inputs S1S0. If D0 = 0, D1 = 1, D2 = A and D3 = A', which function of A, S1 and S0 appears at the output?

AS1'S0 + S1S0'A + S1S0A

BS1'S0 + S1S0'A + S1S0A'

CS1'S0' + S1S0'A + S1S0A'

DS1'S0 + S1S0'A' + S1S0A

13In K-map simplification, a don't-care cell should be included in a group only when it:

Alies diagonally adjacent to a 1-cell

Bconverts the SOP form into POS form

Chelps form a larger valid group and reduces literals

Dmakes every prime implicant essential

14In a synchronous sequential circuit, what is the immediate design purpose of using a common clock for all flip-flops?

AIt makes state changes occur at defined clock instants rather than at arbitrary input-change times.

BIt makes the circuit output independent of the present state.

CIt converts all flip-flops into combinational gates.

DIt removes the need for setup and hold time constraints.

15When minimizing a sum-of-products expression with a Karnaugh map, which grouping rule is correct?

ADiagonal adjacency is sufficient for making a group of two cells.

BEvery 0 must be grouped with the nearest 1 to reduce the expression.

CGroups may contain any convenient number of adjacent 1s.

DGroups should be as large as possible and contain 1, 2, 4, 8, ... adjacent cells, with wrap-around adjacency allowed.

Paper - II (viii) — Digital Logic Systems MCQ - Practice Questions with Answers

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