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Paper - II (ix) — Computer Organization and Architecture MCQ - Practice Questions with Answers

Solve 44 Paper - II (ix) — Computer Organization and Architecture questions for RAS/RPSC preparation.

Practice questions

Q1In a snooping cache-coherence protocol on a shared bus, what do cache controllers monitor?

A Only I/O interrupt priority levels, because cache coherence is an interrupt-scheduling problem
B Bus transactions for memory blocks, so they can detect reads or writes affecting blocks they cache
C Only the program counters of all processors
D The contents of all ALU result registers after every arithmetic operation
Explanation

In snooping protocols, caches observe the bus or other broadcast medium for transactions involving memory blocks. If a transaction refers to a block held locally, the cache controller can invalidate, update, supply data, or change the block state according to the coherence protocol.

Q2Which statement best distinguishes hardwired control from microprogrammed control in a processor?

A Hardwired control stores all control signals as cache lines in main memory.
B Hardwired control is always slower because it must fetch microinstructions.
C Microprogrammed control cannot implement conditional sequencing.
D Microprogrammed control generates control signals by reading microinstructions from a control store.
Explanation

Hardwired control derives control signals through combinational and sequential logic designed for the instruction set. Microprogrammed control instead uses a control memory whose microinstructions describe the lower-level control actions for each instruction step.

Q3In a stored-program Von-Neumann computer, which statement best explains the usual Von-Neumann bottleneck?

A Each I/O device must contain a separate program counter, so the CPU cannot fetch the next instruction.
B The ALU can perform only one arithmetic operation in its lifetime, so every program must be reloaded after each addition.
C The control unit stores all user data permanently, so main memory becomes unnecessary during execution.
D Instructions and data share the same main-memory path, so instruction fetches and data transfers can contend for bandwidth.
Explanation

The Von-Neumann model keeps program instructions and data in read/write main memory and the CPU accesses them through the memory interface. When the same path is used for fetching instructions and moving operands, the processor may wait on memory bandwidth; this contention is called the Von-Neumann bottleneck.

Q4An instruction uses the contents of register R2 as a base and adds a signed displacement field from the instruction to form the memory address. Which addressing mode is being used?

A Implied addressing
B Register direct addressing
C Immediate addressing
D Displacement addressing
Explanation

Displacement addressing forms the effective address by adding a constant field in the instruction to a register value. It is widely used for arrays, records, stack frames, and load-store instructions because it combines a compact instruction field with a relocatable base address.

Q5Two processors in a shared-memory multiprocessor cache the same memory block. Processor P1 writes to that block under a snooping write-invalidate protocol. What should other caches normally do when they observe the invalidate transaction?

A Write a different value to main memory to mark the block as shared.
B Mark their copies of that block invalid so later reads miss and obtain the updated value.
C Silently keep their old copies valid until the operating system schedules them again.
D Change only the program counter, because data-cache coherence is handled by branch prediction.
Explanation

In a snooping coherence design, cache controllers watch bus or interconnect transactions. When a processor gains write permission for a shared block, a write-invalidate protocol makes other cached copies invalid, so a later read cannot use stale data and must fetch a coherent copy.

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More questions

6Two processors have cached the same memory block. Processor P1 wants to write the block under a snooping write-invalidate coherence protocol. What action is most characteristic of this protocol?

AP1 broadcasts an invalidation so other cached copies of that block become invalid
BThe memory block is permanently moved to secondary storage
CP1 silently writes its cache and leaves all other copies valid
DAll processors must first copy the block into their instruction caches

7A processor designer implements control signals using fixed logic gates and decoders rather than a control memory. Which description is most accurate?

AIt is hardwired control, typically fast but less flexible to modify after the datapath is fixed.
BIt eliminates the need for opcode decoding, because all instructions use identical micro-operations.
CIt is impossible to pipeline, because hardwired control cannot produce more than one signal per cycle.
DIt is microprogrammed control, because every signal must be fetched from a writable control store.

8An instruction contains an address field X, and the effective address is obtained by adding X to the current Program Counter. Which addressing mode is being used?

AImmediate addressing
BRegister indirect addressing
CRelative addressing
DDirect addressing

9In a direct-mapped cache with 64 cache lines, block number 130 of main memory will map to which cache line?

ALine 1
BLine 64
CLine 0
DLine 2

10A CPU control unit is implemented using a control store containing microinstructions. Which term best describes this method of generating control signals?

AHardwired control
BMicroprogrammed control
CDirect-mapped control
DInterrupt-driven control

11In DMA transfer, what is the main role of the DMA controller after the CPU initializes the transfer parameters?

AIt permanently disables memory access by the processor.
BIt translates virtual addresses into page table entries for all processes.
CIt executes the user program while the CPU is suspended.
DIt transfers data directly between an I/O device and main memory with limited CPU intervention.

12In a multiprocessor system, what problem does a cache-coherence protocol primarily address?

AIt prevents different caches from indefinitely holding inconsistent copies of the same memory block.
BIt replaces the operating system scheduler for assigning CPU time.
CIt converts all cache misses into hits by increasing cache size.
DIt ensures every processor has the same number of registers.

13For the register-transfer statement R2 <- R1 in a synchronous CPU, which interpretation is correct?

AThe value in R1 is cleared automatically after it is placed on the internal bus
BThe contents of R1 are copied into R2 on the active clock edge, while R1 itself is not destroyed
CThe physical register R1 is renamed as R2 without any data movement
DThe contents of R1 and R2 are exchanged in a single implicit swap operation

14In a single-bus CPU organization, why are temporary registers often required during multi-operand arithmetic operations?

AThe control unit is disabled whenever a register transfer occurs.
BThe bus can carry only one source value at a time, so intermediate operands must be staged.
CThe ALU cannot perform arithmetic unless both operands are stored in main memory.
DThe program counter must be copied into every general-purpose register first.

15Which comparison between hardwired control and microprogrammed control is most accurate for a processor control unit?

AMicroprogrammed control eliminates the need for an instruction register and timing signals
BMicroprogrammed control can only be used in Harvard architecture machines
CHardwired control always stores every control signal pattern in a writable control memory
DHardwired control is generally faster but less flexible, while microprogrammed control is easier to modify for complex instruction sequencing

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