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Paper - II (ix) — Computer Organization and Architecture MCQ — 44 Practice Questions with Answers

Paper - II (ix) — Computer Organization and Architecture is a Computer Systems (Senior CI) topic in the RAS/RPSC syllabus. This page gathers exam-style Paper - II (ix) — Computer Organization and Architecture multiple-choice questions with correct answers and explanations, so aspirants can test recall and revise frequently examined concepts.

Practice 44 Paper - II (ix) — Computer Organization and Architecture multiple-choice questions with detailed answers and explanations. Ideal for RAS/RPSC exam preparation.

44 Questions Computer Systems (Senior CI)

Reviewed by: Aspirant Academy Editorial Team

Practice Questions

Q1. In a snooping cache-coherence protocol on a shared bus, what do cache controllers monitor?

A Only I/O interrupt priority levels, because cache coherence is an interrupt-scheduling problem
B Bus transactions for memory blocks, so they can detect reads or writes affecting blocks they cache Correct
C Only the program counters of all processors
D The contents of all ALU result registers after every arithmetic operation

Explanation

In snooping protocols, caches observe the bus or other broadcast medium for transactions involving memory blocks. If a transaction refers to a block held locally, the cache controller can invalidate, update, supply data, or change the block state according to the coherence protocol.

Q2. Which statement best distinguishes hardwired control from microprogrammed control in a processor?

A Hardwired control stores all control signals as cache lines in main memory.
B Hardwired control is always slower because it must fetch microinstructions.
C Microprogrammed control cannot implement conditional sequencing.
D Microprogrammed control generates control signals by reading microinstructions from a control store. Correct

Explanation

Hardwired control derives control signals through combinational and sequential logic designed for the instruction set. Microprogrammed control instead uses a control memory whose microinstructions describe the lower-level control actions for each instruction step.

Q3. In a stored-program Von-Neumann computer, which statement best explains the usual Von-Neumann bottleneck?

A Each I/O device must contain a separate program counter, so the CPU cannot fetch the next instruction.
B The ALU can perform only one arithmetic operation in its lifetime, so every program must be reloaded after each addition.
C The control unit stores all user data permanently, so main memory becomes unnecessary during execution.
D Instructions and data share the same main-memory path, so instruction fetches and data transfers can contend for bandwidth. Correct

Explanation

The Von-Neumann model keeps program instructions and data in read/write main memory and the CPU accesses them through the memory interface. When the same path is used for fetching instructions and moving operands, the processor may wait on memory bandwidth; this contention is called the Von-Neumann bottleneck.

Q4. An instruction uses the contents of register R2 as a base and adds a signed displacement field from the instruction to form the memory address. Which addressing mode is being used?

A Implied addressing
B Register direct addressing
C Immediate addressing
D Displacement addressing Correct

Explanation

Displacement addressing forms the effective address by adding a constant field in the instruction to a register value. It is widely used for arrays, records, stack frames, and load-store instructions because it combines a compact instruction field with a relocatable base address.

Q5. Two processors in a shared-memory multiprocessor cache the same memory block. Processor P1 writes to that block under a snooping write-invalidate protocol. What should other caches normally do when they observe the invalidate transaction?

A Write a different value to main memory to mark the block as shared.
B Mark their copies of that block invalid so later reads miss and obtain the updated value. Correct
C Silently keep their old copies valid until the operating system schedules them again.
D Change only the program counter, because data-cache coherence is handled by branch prediction.

Explanation

In a snooping coherence design, cache controllers watch bus or interconnect transactions. When a processor gains write permission for a shared block, a write-invalidate protocol makes other cached copies invalid, so a later read cannot use stale data and must fetch a coherent copy.

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Frequently Asked Questions

How many Paper - II (ix) — Computer Organization and Architecture MCQ questions are available?
There are 44 Paper - II (ix) — Computer Organization and Architecture practice MCQs available on Aspirant Academy, with detailed answers and explanations for each question.
Are answers and explanations provided for Paper - II (ix) — Computer Organization and Architecture MCQs?
Yes, every Paper - II (ix) — Computer Organization and Architecture question comes with the correct answer and a detailed explanation to help you understand the underlying concept.
How is Paper - II (ix) — Computer Organization and Architecture relevant to the RAS/RPSC exam?
Paper - II (ix) — Computer Organization and Architecture falls under the Computer Systems (Senior CI) section of the RAS/RPSC syllabus. It is a frequently tested area and regular practice with these MCQs will strengthen your preparation.
Can I practice Paper - II (ix) — Computer Organization and Architecture questions in Hindi?
Yes, Aspirant Academy offers bilingual support. You can practice Paper - II (ix) — Computer Organization and Architecture MCQs in both English and Hindi, including questions, options, and explanations.

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