MCQ
Paper - II (vii) — Computer Organization and Operation System MCQ - Practice Questions with Answers
Solve 56 Paper - II (vii) — Computer Organization and Operation System questions for RAS/RPSC preparation.
Practice questions
Q1A direct-mapped cache has 64 lines, each line stores 32 bytes, and physical addresses are 24 bits. For a byte-addressable memory, how many bits are used for tag, line index, and block offset respectively?
The block offset identifies a byte inside a 32-byte line, so it needs log2(32) = 5 bits. A direct-mapped cache with 64 possible lines needs log2(64) = 6 index bits. The physical address is 24 bits, so the remaining 24 - 5 - 6 = 13 bits form the tag used to test whether the indexed line is the requested block.
Q2An 8-bit ALU adds 0111 1011 and 0100 1110, treating the operands as two's-complement signed integers. Which flag interpretation is correct?
The binary sum is 1100 1001, which is 201 if unsigned but -55 if interpreted as 8-bit two's complement. Since 123 and 78 are both positive signed operands, the negative signed result indicates overflow. Because 201 is below 256, no carry out of bit 7 is generated.
Q3A system has total resources (A, B, C) = (10, 5, 7). For processes P0-P4, Allocation/Max are: P0 (0,1,0)/(7,5,3), P1 (2,0,0)/(3,2,2), P2 (3,0,2)/(9,0,2), P3 (2,1,1)/(2,2,2), P4 (0,0,2)/(4,3,3). Which sequence is a safe sequence under the Banker's algorithm?
The currently available vector is total minus allocated: (10,5,7) - (7,2,5) = (3,3,2). P1 needs (1,2,2), so it can finish and release (2,0,0), making (5,3,2). P3 then needs (0,1,1), P4 needs (4,3,1), P0 needs (7,4,3) after those releases, and finally P2 needs (6,0,0). Therefore P1, P3, P4, P0, P2 is safe.
Q4In a demand-paged operating system, a page fault occurs while a process is executing in user mode. Which sequence best describes what happens before the faulting instruction can complete?
A page fault is an exception handled by the operating system. If the virtual address is legal but the page is not resident, the OS selects or allocates a frame, reads the page from backing store, records the valid mapping, and resumes execution so that the instruction that faulted can be retried.
Q5A CPU has separate interrupt-enable and interrupt-pending bits. An I/O device finishes a transfer while interrupts are disabled. Which behaviour is most consistent with interrupt-driven I/O?
Interrupt-driven I/O allows a device to signal that it needs attention, but processors commonly provide masking or enable bits to protect critical sections. If the request is maskable and interrupts are disabled, the event is not serviced immediately. A pending indication lets the processor recognize and handle the interrupt later, subject to priority and enable rules.
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More questions
6Two directory entries are hard links to the same regular file on a Unix-like file system. Which statement is necessarily true before either link is removed?
7In 8-bit two's-complement arithmetic, the CPU adds 0111 0100 and 0101 1001. Which result and overflow interpretation is correct?
8During the fetch phase of a simple stored-program CPU, which register-level sequence is most consistent with fetching the next instruction from main memory?
9A direct-mapped cache has 64 lines, each line holding 16 bytes. For a 32-bit byte address, which tag-index-offset split is correct?
10Which statement best distinguishes DMA-based I/O from programmed I/O for transferring a large disk block into main memory?
11A single-threaded process running on a uniprocessor issues a blocking read system call for disk data that is not yet available. Which process-state transition is most accurate until the disk interrupt reports completion?
12A system uses 32-bit virtual addresses, 4 KB pages, and a two-level page table with 10 bits for the outer page-table index and 10 bits for the inner index. What is the virtual page number and page offset for virtual address 0x12345ABC?
13A paged system has a TLB lookup time of 20 ns and a main-memory access time of 100 ns. The TLB hit ratio is 90 percent. Assume no page faults, no cache, and that a TLB miss requires one memory access to read the page-table entry and one memory access to read the required word. What is the effective memory access time?
14A cache has hit time 2 ns, miss penalty 48 ns, and hit ratio 90%. What is the average memory access time, assuming miss penalty is additional time after the cache lookup?
15For the reference string 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 with initially empty frames, which observation correctly illustrates Belady's anomaly under FIFO page replacement?